HyGCN: A GCN Accelerator with Hybrid Architecture
HyGCN: A GCN Accelerator with Hybrid Architecture
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DOI：
10.1109/hpca47549.2020.00012
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发表时间：
2020-01
期刊：
影响因子：
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通讯作者：
Mingyu Yan;Lei Deng;Xing Hu;Ling Liang;Yujing Feng;Xiaochun Ye;Zhimin Zhang;Dongrui Fan;
中科院分区：
文献类型：
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作者：
Mingyu Yan;Lei Deng;Xing Hu;Ling Liang;Yujing Feng;Xiaochun Ye;Zhimin Zhang;Dongrui Fan;
受神经网络巨大成功的启发，图卷积神经网络（GCN）被提出来分析图数据。GCN主要包括具有不同执行模式的两个阶段。聚合阶段，表现为图形处理，显示动态和不规则的执行模式。组合阶段更像神经网络，呈现静态和规则的执行模式。GCN的混合执行模式需要一种消除不规则性并利用规则性的设计。此外，为了实现更高的性能和能源效率，设计需要利用聚合阶段中的高顶点内并行性，组合阶段中的高度可重用的顶点间数据，以及由GCN的新特性引入的融合逐阶段执行的机会。然而，现有的架构无法满足这些需求。在这项工作中，我们首先描述了GCN在Intel Xeon CPU上的混合执行模式。在此基础上，我们设计了一个GCN加速器HyGCN，采用混合架构来有效地执行GCN。具体来说，首先，我们建立了一个新的编程模型，利用我们的硬件设计的细粒度并行。其次，我们提出了一种硬件设计，具有两个高效的处理引擎，以减轻聚合阶段的不规则性，并利用合并阶段的规则性。此外，这些引擎可以利用各种并行性并有效地重用高度可重用的数据。第三，我们通过引擎间流水线进行阶段间融合和基于优先级的片外存储器访问协调来优化整个系统，以提高片外带宽利用率。与运行在Intel Xeon CPU和NVIDIA V100 GPU上的最先进的软件框架相比，我们的工作分别实现了平均1509倍的加速比和平均6.5倍的加速比，分别降低了2500倍和10倍的能耗。
Inspired by the great success of neural networks, graph convolutional neural networks (GCNs) are proposed to analyze graph data. GCNs mainly include two phases with distinct execution patterns. The Aggregation phase, behaves as graph processing, showing a dynamic and irregular execution pattern. The Combination phase, acts more like the neural networks, presenting a static and regular execution pattern. The hybrid execution patterns of GCNs require a design that alleviates irregularity and exploits regularity. Moreover, to achieve higher performance and energy efficiency, the design needs to leverage the high intra-vertex parallelism in Aggregation phase, the highly reusable inter-vertex data in Combination phase, and the opportunity to fuse phase-by-phase execution introduced by the new features of GCNs. However, existing architectures fail to address these demands. In this work, we first characterize the hybrid execution patterns of GCNs on Intel Xeon CPU. Guided by the characterization, we design a GCN accelerator, HyGCN, using a hybrid architecture to efficiently perform GCNs. Specifically, first, we build a new programming model to exploit the fine-grained parallelism for our hardware design. Second, we propose a hardware design with two efficient processing engines to alleviate the irregularity of Aggregation phase and leverage the regularity of Combination phase. Besides, these engines can exploit various parallelism and reuse highly reusable data efficiently. Third, we optimize the overall system via inter-engine pipeline for inter-phase fusion and priority-based off-chip memory access coordination to improve off-chip bandwidth utilization. Compared to the state-of-the-art software framework running on Intel Xeon CPU and NVIDIA V100 GPU, our work achieves on average 1509× speedup with 2500× energy reduction and average 6.5× speedup with 10× energy reduction, respectively.