Exploiting thread and data level parallelism for ultimate parallel SystemC simulation
Exploiting thread and data level parallelism for ultimate parallel SystemC simulation
复制标题
利用线程和数据级并行性实现终极并行 SystemC 仿真
DOI：
10.1145/3061639.3062243
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
R. Dömer
中科院分区：
文献类型：
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作者：
T. Schmidt;Guantao Liu;R. Dömer
大多数并行SystemC方法有两个限制：(A)用户必须手动分离所有并行线程，以避免由于争用条件造成的数据损坏，以及(B)未利用可用的硬件向量单元。在本文中，我们提出了一个高级编译器基础设施，用于在线程级自动并行化SystemC模型。此外，我们的基础设施还利用了数据级并行化的机会。我们的实验结果表明，N×M的加速比接近线性，其中N和M分别表示线程级和数据级因素。反过来，4核多处理器的加速比高达8.8倍，60核至强Phi处理器的加速比高达212倍。
Most parallel SystemC approaches have two limitations: (a) the user must manually separate all parallel threads to avoid data corruption due to race conditions, and (b) available hardware vector units are not utilized. In this paper, we present an advanced compiler infrastructure for automatic parallelization of SystemC models at the thread-level. In addition, our infrastructure exploits opportunities for data-level parallelization. Our experimental results show a nearly linear speedup of N×M, where N and M denote the thread and data-level factors, respectively. In turn, a 4-core multi-processor achieves a speedup of up to 8.8×, and a 60-core Xeon Phi processor reaches up to 212×.