The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
复制标题
具有嵌入式浮点运算单元的 FPGA 中的粗粒度/细粒度逻辑接口
DOI：
10.1155/2008/736203
复制
发表时间：
2008
影响因子：
4.3
通讯作者：
Yu C
中科院分区：
文献类型：
--
作者：
Yu C
本文研究了FPGA中细粒度和粗粒度可编程逻辑之间的接口。具体而言，它提出了一个实证研究，涵盖了位置，引脚排列，以及嵌入式浮点单元（FPU）和FPGA中的细粒度逻辑结构之间的互连。同时研究了在同时包含FPGA和嵌入式存储器的FPGA中的这种接口。结果表明：（1）FPU应具有正方形纵横比;（2）它们应位于FPGA中心附近;（3）它们的I/O引脚应围绕FPU的所有四边排列;（4）嵌入式存储器应位于FPU之间;（5）连接较高I/O密度的粗粒度块会增加对路由资源的需求。具有嵌入式存储器的混合FPGA需要比不使用嵌入式存储器的情况宽12%的通道。
This paper examines the interface between fine‐grained and coarse‐grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine‐grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse‐grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.