Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM
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DOI：
10.1109/tcsi.2015.2403031
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发表时间：
2015-04
期刊：
影响因子：
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通讯作者：
Minjie Lv;Hongbin Sun;Qiwei Ren;Ting Yu;J. Xin;Nanning Zheng
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文献类型：
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作者：
Minjie Lv;Hongbin Sun;Qiwei Ren;Ting Yu;J. Xin;Nanning Zheng
三维（3D）集成有望为3D逻辑- dram集成计算系统提供显着的性能和能效提高，但也对良率提出了重大挑战。为了解决这一挑战，本文探索了一种利用逻辑-DRAM协同设计来重新激活未使用的备件的方法，从而使成本效益技术能够在芯片堆叠后修复3D集成引起的缺陷DRAM单元。特别是，我们建议通过一个小的架构修改，使DRAM阵列的备用存储器向片外访问开放，并在逻辑芯片上进一步设计具有有效架构的缺陷地址比较和冗余地址重映射，以实现等效的存储器修复。仿真结果表明，所提出的堆叠DRAM修复技术可以显著减轻潜在的良率损失，且面积和功耗开销最小，时间损失可以忽略不计。
Three-dimensional (3D) integration is promising to provide dramatic performance and energy efficiency improvement to 3D logic-DRAM integrated computing system, but also poses significant challenge to the yield. To address this challenge, this paper explores a way to leverage logic-DRAM co-design to reactivate unused spares and thereby enable the cost-efficient technique to repair 3D integration-induced defective DRAM cells after die stacking. In particular, we propose to make the DRAM array open its spares to off-chip access by a small architectural modification and further design the defective address comparison and redundant address remapping with an efficient architecture on logic die to achieve equivalent memory repair. Simulation results demonstrate that the proposed repair technique for stacked DRAM can significantly alleviate potential yield loss, with minimal area and power consumption overhead and negligible timing penalty.