A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems
A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems
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DOI：
10.1109/tcsi.2006.883854
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发表时间：
2006-12
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影响因子：
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通讯作者：
Shuenn-Yuh Lee;Chih-Jen Cheng
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文献类型：
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作者：
Shuenn-Yuh Lee;Chih-Jen Cheng
提出了一种适用于生物微系统的10位动态范围超低压低功耗自适应Σ-Δ模数转换器（SDADC）。该SDADC包括开关电流Σ-Δ调制器（SISDM）和数字抽取器。为了实现低电压的要求，采用了一种新型的AB类开关电流存储单元来实现SISDM，过采样比（OSR）为64。此外，建议的差分电流比较器和低电压1位开关电流数模转换器（SIDAC）的SDM的设计。来自使用AB类存储器单元的SISDM的益处是低功耗和高动态范围。此外，提出了一种新的单乘法器结构来实现有限脉冲响应（FIR）数字滤波器，这是在抽取器的主要硬件元件。对于具有不同生物信号频率的各种应用，SDADC可以在不同的操作模式下操作。整体ADC已实现在台积电0.18妈妈1 P6 M标准CMOS工艺技术。测量结果表明，当输入信号为1.25kHz的正弦波，带宽为5 kHz时，在0.8V单电源供电下，SISDM的动态范围大于60 dB，功耗为180 μ W。此外，对包括SISDM和抽取器的SDADC进行了布局后仿真，结果表明，在不降低数字电路性能的情况下，SDADC的动态范围仍大于60 dB
An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented. The proposed SDADC includes a switched-current sigma-delta modulator (SISDM) and a digital decimator. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the oversampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class-AB memory cell are low power consumption and high dynamic range. Moreover, a new single-multiplier structure is presented to implement the finite-impulse-response (FIR) digital filters which are the major hardware elements in the decimator. For the various applications with different biosignal frequencies, the SDADC could be manipulated in different operating modes. The overall ADC has been implemented in a TSMC 0.18-mum 1P6M standard CMOS process technology. Without a voltage booster to raise the gate voltage of switches, measurement results show that the SISDM has a dynamic range over 60 dB and a power consumption of 180 muW with an input signal of 1.25-kHz sinusoid wave and 5-kHz bandwidth under a single 0.8-V power supply for electroneurography signals. In addition, the postlayout simulations of SDADC including SISDM and decimator reveal that the dynamic range is still over 60 dB without degrading by digital circuits