iTimerC: Common path pessimism removal using effective reduction methods
iTimerC: Common path pessimism removal using effective reduction methods
复制标题
iTimerC：使用有效的减少方法消除悲观主义的常见路径
DOI：
--
复制
发表时间：
2014
期刊：
影响因子：
--
通讯作者：
I. Jiang
中科院分区：
文献类型：
--
作者：
Yu;Yu;I. Jiang
静态时序分析是现代集成电路设计中保证时序收敛的关键环节。然而，快速增长的设计复杂性和增加的片上变化使该过程复杂化。为了捕获设计的更准确的时序性能，普遍存在公共路径悲观去除以消除时序分析期间时钟路径中人为引起的悲观。为了避免在设计中对所有路径进行详尽的探索，本文提出了一种新的时序分析框架，该框架基于基于块的静态时序分析，时序图简化和动态边界来消除公共路径悲观。实验结果表明，该方法是高度可扩展的，特别是与大规模设计的运行时间短。此外，我们的方法优于TAU 2014计时竞赛的获胜者，生成准确的结果，并实现超过2.13倍的加速。
Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this paper, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, and dynamic bounding. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.