A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors
A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors
复制标题
多核和多线程微处理器中基于缓存的侧通道的预测模型
DOI：
10.1007/978-3-642-14706-7_6
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
D. Ponomarev
中科院分区：
文献类型：
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作者：
Leonid Domnitser;N. Abu;D. Ponomarev
侧通道是一种信息通道，它无意中传递有关程序的信息，作为实现的副作用。最近的研究已经说明了使用共享高速缓存作为侧通道来从计算安全的密码应用中提取私钥。该高速缓存侧信道在攻击者检测关键数据的高速缓存泄漏的能力受到时序问题的限制的意义上是不完美的。此外，一些检测到的泄漏是由于非关键数据。因此，由于旁道的不完善性，很难评估脆弱程度。类似地，当采用进一步降低信道质量但不一定完全关闭信道的解决方案时，难以评估其有效性。为了满足这一需求，本文提出了一个数学模型来评估预期泄漏的缓存作为一个函数的该高速缓存参数和受害者的应用程序的行为。我们使用模拟来量化这些参数为典型的攻击场景，以验证模型。我们证明，该模型准确地估计侧通道泄漏的AES和Blowfish加密和解密的各种缓存配置。
A side channel is an information channel that unintentionally communicates information about a program as a side effect of the implementation. Recent studies have illustrated the use of shared caches as side channels to extract private keys from computationally secure cryptographic applications. The cache side channel is imperfect in the sense that the attacker's ability to detect cache leakage of critical data is limited by the timing issues. Moreover, some detected leakages are due to non-critical data. Thus, it is difficult to assess the degree of vulnerability given the imperfect nature of the side-channel. Similarly, when solutions that further degrade the quality of the channel, but do not necessarily close it completely, are employed, it is difficult to evaluate their effectiveness. To address this need, this paper proposes a mathematical model to evaluate the expected leakage in a cache as a function of the cache parameters and the victim application behavior. We use simulation to quantify these parameters for typical attack scenarios to validate the model. We demonstrate that the proposed model accurately estimates side channel leakage for for AES and Blowfish encryption and decryption on a variety of cache configurations.