On the implementation of 128-pt FFT/IFFT for high-performance WPAN
On the implementation of 128-pt FFT/IFFT for high-performance WPAN
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关于高性能WPAN的128点FFT/IFFT的实现
DOI：
10.1109/iscas.2005.1465885
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
K. Paul
中科院分区：
文献类型：
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作者：
C. Huggett;K. Maharatna;K. Paul
研究了一种适用于无线个人区域网(WPAN)IEEE 802.15.3a标准的128点FFT/IFFT处理器的高效实现。128点FFT/IFFT结构是通过将其分解为一个8点和一个16点FFT而设计的。对16点FFT进行了重新分解，提出了8/SPL次/4/SPL次/4和8/SPL次/2/SPL次/8两种不同的128点FFT算法，并从算法和实现的角度分析了它们的优缺点。该体系结构已在Virtex II系列的现场可编程门阵列上实现。结果表明，8/SPL Times/2/SPL Times/8结构更适合于所述目的。
The paper deals with the efficient realization of a 128-pt FFT/IFFT processor for application in the IEEE 802.15.3a standard for wireless personal area networks (WPAN). The 128-pt FFT/IFFT architecture has been designed by devolving it into one 8-pt and one 16-pt FFT. The 16-pt FFT was decomposed again and two separate 128-pt FFT algorithms have been developed, viz., 8/spl times/4/spl times/4 and 8/spl times/2/spl times/8. Their relative merits and demerits have been analyzed from the algorithm and implementation points of view. The architectures have been prototyped on a Virtex II FPGA. The results indicate that the 8/spl times/2/spl times/8 architecture is better suited for the stated purpose.