Development of a standard cell library and ASPEC design flow for Organic Thin Film Transistor technology
Development of a standard cell library and ASPEC design flow for Organic Thin Film Transistor technology
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开发有机薄膜晶体管技术的标准单元库和 ASPEC 设计流程
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
L. Terés
中科院分区：
文献类型：
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作者：
M. Mashayekhi;M. Llamas;J. Carrabina;J. Pallares;F. Vila;L. Terés
专用印刷电子电路（ASPEC）是为特殊应用而设计和定制的电路，而不是通用用途，是ASIC的等效术语，但用于印刷电子。在本文中，我们通过开发CPI（工艺创新中心）技术的标准单元库，将印刷电子扩展到ASPEC设计，该标准单元库的基板是柔性PEN（50微米厚），使用PDMS绑定工艺层压到玻璃上。标准单元拓扑允许使用自动化布局和布线工具实现布局设计过程的完全自动化。此外，标准单元显著有助于加快电路开发时间，因为可以使用库从高级描述（Verflog，VHDL）合成块。单元库是针对两种不同类型的顶栅底接触有机薄膜晶体管（OTFT）生成的：1）叉指型OTFT，2）Corbino OTFT。由于只有p沟道晶体管可用，因此将伪比例pMOS lodic用于电路。开发的库包括7门：5个组合门（反相器，NAND 2，NAND 3，NAND 4和XOR 2）和2个顺序门（D触发器和使能D触发器）和一个FEED单元。采用Glade版图编辑器和MaskEngineer4.8.4以及AIMSpice仿真器对单元版图进行了设计和单元电路仿真。从布局中自动提取电气互连，以实现布局与原理图（LVS）。最后，我们设计并制作了一个使用组合电路的井字游戏，并将其特性化以展示标准单元库。
Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): 1)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.