Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation
Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation
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DOI：
10.1109/apccas50809.2020.9301704
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发表时间：
2020-12
期刊：
影响因子：
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通讯作者：
Yuka Nakamatsu;T. Kihara
中科院分区：
文献类型：
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作者：
Yuka Nakamatsu;T. Kihara
传统的直接射频(RF)采样接收器不能根据输入信号的功率动态地降低其功耗。动态降低使他们能够将运行期间的总功耗降低到无线终端所需的水平。我们降低了直接射频采样接收器中时间交错 ADC (TI-ADC) 之后的一阶递归级联积分梳状 (CIC) 滤波器中抽取器的时钟频率，检测到比所需灵敏度更高的输入信号功率。尽管抽取会稍微降低接收器的输出信噪比 (SNR)，但它会降低数字构建模块的功耗。我们使用 65 nm CMOS 工艺设计了一款 3.68 GS/s 直接 RF 采样接收器，包括模拟和数字模块，适用于 Sub-GHz 应用。仿真表明，接收器在抽取因子为 8 的情况下将功耗降低了 10.6 mW 至 9.6 mW，同时将输出 SNR 提高了 0.9 dB。这意味着当接收器接收到高于所需水平的输入功率时，可以降低功耗，而不降低输出 SNR。
The conventional direct radio frequency (RF) sampling receivers can not reduce their power consumption dynamically according to the power of input signals. The dynamic reduction enables them to decrease the total power consumption during operation to the level required for wireless terminals. We decrease the clock frequency of decimators in first-order recursive cascaded integrator-comb (CIC) filters after a time-interleaved ADC (TI-ADC) in a direct-RF sampling receiver, detecting higher power of input signals than the required sensitivity. Although the decimation slightly degrades the output signal-to-noise ratio (SNR) of the receiver, it reduces the power consumption of the digital building blocks. We design a 3.68-GS/s direct-RF sampling receiver, including analog and digital blocks, for Sub-GHz applications by using a 65-nm CMOS process. Simulations show that the receiver reduces a power consumption of 10.6 mW to 9.6 mW with a decimation factor of eight, whereas increasing the output SNR by 0.9 dB. This means that the receiver can decrease the power consumption, not degrading the output SNR, when receiving higher input power than the required level.