A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems
复制标题
多核混合时间关键系统的 DRAM 内存访问调度框架
DOI：
10.1109/rtas.2015.7108454
复制
发表时间：
2015
期刊：
影响因子：
--
通讯作者：
R. Pellizzoni
中科院分区：
文献类型：
--
作者：
Mohamed Hassan;Hiren D. Patel;R. Pellizzoni
混合时间关键系统是同时适应硬实时(HRT)和软实时(SRT)任务的实时系统。HRT任务要求保证最差延迟，而SRT任务有平均情况带宽(BW)需求。混合时间关键系统中的内存请求通常具有不同的事务大小，具体取决于发布者任务是HRT还是SRT。例如，HRT任务通常发出具有缓存行大小的请求。另一方面，SRT任务可能发出大小为KB的请求。来自多媒体核、控制网络接口的核和直接存储器访问(DMA)的请求就是这些大容量请求的明显例子。基于这些观察结果，我们在这项工作中提出了一种新的内存请求调度方法。此方法在大型请求中保留局部性，以最大限度地减少最坏情况下的延迟，同时保持所需的平均情况下的BW。为了实现这一目标，我们引入了一种新颖紧凑的时分复用调度器，该调度器适合于混合时间关键系统。我们还提出了一种新的框架，它为多核混合时间关键系统构造了最优的片外DRAM存储控制器调度。这些时间表在启动时加载到内存控制器。根据建议的时间表，我们提供了详细的静态分析，以确保可预测性。通过综合实验和一个多媒体系统的实际应用案例，我们将所提出的控制器与最先进的实时存储控制器进行了比较。
Mixed-time critical systems are real-time systems that accommodate both hard real-time (HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase latency, while SRT tasks have average-case bandwidth (BW) demands. Memory requests in mixed-time critical systems usually have different transaction sizes based on whether the issuer task is HRT or SRT. For example, HRT tasks often issue requests with a cache line size. On the other side, SRT tasks may issue requests with a size of KBs. Requests from multimedia cores, cores controlling network interfaces and direct memory accesses (DMAs) are obvious examples of these large-size requests. Based on these observations, we promote in this work a new approach to schedule memory requests. This approach retains locality within large-size requests to minimize the worst-case latency, while maintaining the average-case BW as high as required. To achieve this target, we introduce a novel and compact time-division-multiplexing scheduler that is adequate for mixed-time critical systems. We also present a novel framework that constructs optimal offchip DRAM memory controller schedules for multi-core mixedtime critical systems. These schedules are loaded to the memory controller during boot-time. Based on the proposed schedule, we provide a detailed static analysis that guarantees predictability. We compare the proposed controller against state-of-the-art realtime memory controllers using synthetic experiments as well as a practical use-case from multimedia systems.