Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
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DOI：
10.1109/led.2002.1004236
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发表时间：
2002-08
影响因子：
4.9
通讯作者：
M. Ker;Chien‐Hui Chang
中科院分区：
文献类型：
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作者：
M. Ker;Chien‐Hui Chang
提出了一种堆叠nmos触发的可控硅（SNTSCR）作为静电放电（ESD）箝位器件，用于保护CMOS集成电路的混合电压I/O缓冲器。该SNTSCR器件与一般CMOS工艺完全兼容，无需使用厚栅极氧化物来克服栅极氧化物可靠性问题。在0.35 /spl mu/m CMOS工艺下，研究了不同布局参数下SNTSCR器件的ESD稳健性。该SNTSCR器件的器件尺寸仅为60 /spl mu/m/0.35 /spl mu/m，可将堆叠nmos通道宽度为120 /spl mu/m的混合电压I/O缓冲器的HBM ESD电平从原来的/spl sim/2 kV明显提高到大于8 kV。
A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using a thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35 /spl mu/m CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 /spl mu/m can be obviously improved from the original /spl sim/2 kV to be greater than 8 kV by this SNTSCR device with device dimensions of only 60 /spl mu/m/0.35 /spl mu/m.