An approach to approximate computing: Logic transformations for one-minterm changes in specification
An approach to approximate computing: Logic transformations for one-minterm changes in specification
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一种近似计算方法：规格中的一次变化的逻辑转换
DOI：
10.1109/hldvt.2017.8167469
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
Fujita Masahiro
中科院分区：
文献类型：
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作者：
Hari Mohan Gaur;Ashutosh Kumar Singh;Anand Mohan;Masahiro Fujita;Dhiraj K. Pradhan;Kentaro Sano;Fujita Masahiro
这里我们考虑近似计算的一种特殊情况。给定真值表及其相应的多级逻辑电路实现中的规范S，仅通过将真值表值从0改变为1或从1改变为0的恰好一个最小项来将I、S改变为S'。这是近似逻辑综合的一种基本运算，因为函数的变化是最小的（只有一分钟）。我们通过实验证明，即使我们改变电路中所有门的函数，I，而不改变它们的输入信号（它们的即时扇入），即，没有拓扑变化，电路永远不会变得与我们尝试的所有情况下的S'相等。然而，如果我们允许仅改变电路的最后一级I中的一个门的功能，并且也允许改变其输入信号，则电路在平均约13%的情况下变得等效于S'，其中在最后一级中的门平均具有额外的1.1个输入。我们还实验表明，一个minterm的变化真值表相比，一个和两个产品的变化，其中所有的minterms内的产品发生变化，最困难的问题，以适应从工程变更单（ECO）或逻辑调试的观点，当电路实现为多级逻辑。
Here we consider one special situation for approximate computing. Given a specification, S, in a truth table and its corresponding multi-level logic circuit implementation, I, S is changed to S' by only changing the truth table value for exactly one minterm from 0 to 1 or 1 to 0. We would like to transform I into I' in such a way that I' is equivalent to S' This is a sort of basic operations for approximate logic synthesis, as the functional changes are minimal (only for one minterm). We experimentally show that even if we change functions for all of the gates in the circuit, I, without changing their input signals (their immediate fanins), i.e., no topological changes, the circuit can never become equivalent to S' for all the cases we tried. However, if we allow to change the function of only one gate in the last level of the circuit, I, and allow to change its input signals as well, the circuit becomes equivalent to S' around 13% of the cases in average with in average additional 1.1 inputs to the gate in the last level. We also experimentally show that one minterm changes in truth tables are, comparing with one and two products changes where all minterms inside the products are changed, the most difficult problems to accommodate from the viewpoint of Engineering Change Order (ECO) or logic debugging, when the circuits are implemented as multi-level logic.