Analysis and design of high order digital phase locked loops
Analysis and design of high order digital phase locked loops
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高阶数字锁相环分析与设计
DOI：
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发表时间：
2008
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通讯作者：
B. Daniels
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文献类型：
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作者：
B. Daniels
锁相环（PLL）是许多电子设备的重要组成部分；它可以用作频率合成器、时钟数据恢复以及幅度和频率解调器。它本质上是一个非线性闭环反馈系统；非线性主要是由于反馈环路比较器在其输出端表现出类似量化的效应。这种非线性的后果是缺乏对 PLL 环路行为的理解，特别是高阶 PLL 系统的行为和稳定性。
本论文提出了一种带有电荷泵相位频率检测器组件的高阶数字 PLL (DPLL) 系统的新设计技术，为使用模拟 PLL 的线性化模型来分析 DPLL 的常见设计实践提供了替代方案。线性模型只能适用于接近锁定的低阶 DPLL 系统。这是因为 DPLL
系统循环阶数和复杂性增加，线性模型变得越来越不准确，因此高阶数被认为是有风险的。高阶 DPLL 环路的优点是输出信号更纯净，抖动更小，因此频谱效率更高，使其非常理想。
这里利用三种新颖的设计技术实现了高阶 DPLL 系统的设计。一、降低高阶系统方程的复杂度
通过在环路滤波电容器上引入电荷的近似值。其次，非线性是使用分段线性模型建模的，因此复杂性
通过仅根据状态空间中的前几个样本确定系统稳定性和锁定时间，可以进一步简化模型。最后，为了减少随着环路阶数增加所需的设计变量的数量，引入了仅需要一个参数的滤波器原型，并得到了系统极点的最佳放置结果。实施上述方法的结果是可以克服对系统阶数的数学限制并且可以准确地确定高阶DPLL系统的稳定性。
The Phase Locked Loop (PLL) is an important component of many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery, and as amplitude and frequency demodulators. It is an inherently nonlinear closed loop feedback system; the nonlinearity is due mainly to the fact that the feedback loop comparator exhibits quantization-like effects at its output. The consequence of this nonlinearity is a lack of understanding of the behaviour of the PLL loop, particularly the behaviour and stability of high order PLL systems.
This thesis presents a new design technique for high order Digital PLL (DPLL)systems with a charge pump phase frequency detector component, offering an alternative to the common design practice which is to analyze the DPLL using a linearised model of the analogue PLL. The linear model can only be justified for low order DPLL systems that are close to lock. This is due to the fact that as the DPLL
systems loop order and complexity increases the linear model becomes increasingly inaccurate, thus high orders are considered risky. The benefit of a high order DPLL loop is a purer output signal with less jitter and therefore better spectral efficiency making them highly desirable.
The design of high order DPLL systems is realised here by utilising three novel design techniques. First, the complexity of the high order system equation is reduced
by introducing an approximation of charge on the loop filter capacitors. Second, the nonlinearity is modelled using a piecewise linear model, thus the complexity of the
model is further reduced by determining the system stability and lock time from only the first few samples in state space. Finally, to reduce the number of design variables that are required as the loop order is increased, filter prototypes, which only require one parameter, are introduced with the result of optimally placing the system poles. The consequence of implementing the above methodologies is that the mathematical restriction on the system order can be overcome and the stability of high order DPLL systems can be accurately determined.