A low specific on-resistance SOI MOSFET with dual gates and a recessed drain
A low specific on-resistance SOI MOSFET with dual gates and a recessed drain
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DOI:
10.1088/1674-1056/22/2/027304
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发表时间:
2013-02
影响因子:
1.7
通讯作者:
X. Luo;Luo Yinchun;Fan Ye;Gangyi Hu;Wang Xiaowei;Zhengyuan Zhang;Fan Yuanhang;Cai Jinyong;Pei Wang;K. Zhou
中科院分区:
文献类型:
--
作者:
X. Luo;Luo Yinchun;Fan Ye;Gangyi Hu;Wang Xiaowei;Zhengyuan Zhang;Fan Yuanhang;Cai Jinyong;Pei Wang;K. Zhou
A low specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce Ron,sp and maintain a high breakdown voltage (BV). The BV of 233 V and Ron,sp of 4.151 mΩcm2 (VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.