High performance fully-depleted tri-gate CMOS transistors
High performance fully-depleted tri-gate CMOS transistors
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DOI：
10.1109/led.2003.810888
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发表时间：
2003-04-01
影响因子：
4.9
通讯作者：
Chau, R
中科院分区：
文献类型：
--
作者：
Doyle, BS;Datta, S;Chau, R
已在 SOI 衬底上制造出物理栅极长度为 60 nm 的全耗尽 (FD) 三栅极 CMOS 晶体管。这些器件由绝缘层上的顶部栅极和两个侧栅极组成。这些晶体管表现出近乎理想的亚阈值梯度和出色的 DIBL 行为，并且具有比迄今为止报道的任何非平面器件更大的驱动电流特性，可实现正确的目标阈值电压。三栅极器件还表现出在硅体尺寸上的完全耗尽，其尺寸大约比单栅极 SOI 或类似栅极长度的非平面双栅极 SOI 大 1.5-2 倍，这表明这些器件更容易使用传统制造工具制造。将三栅极晶体管与相同技术节点的传统体 CMOS 器件进行比较，发现这些非平面器件与类似尺寸的体 CMOS 晶体管具有竞争力。此外，对晶体管栅极长度低至 30 nm 的三栅极晶体管的三维 (3-D) 模拟表明，30 nm 三栅极器件仍然完全耗尽，具有接近理想的亚阈值摆幅和出色的短沟道特性，这表明三栅极晶体管在不久的将来可能成为体晶体管的可行替代品。
Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5-2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.