Integrated Flow for Reverse Engineering of Nanoscale Technologies
Integrated Flow for Reverse Engineering of Nanoscale Technologies
复制标题
纳米技术逆向工程集成流程
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
H. Graeb
中科院分区：
文献类型：
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作者：
Bernhard Lippmann;Michael Werner;Niklas Unverricht;Aayush Singla;P. Egger;Anja Dübotzky;H. Gieser;M. Rasche;Oliver Kellermann;H. Graeb
鉴于盗版和恶意操纵采用45纳米及以下技术的复杂集成电路的潜在风险，越来越需要一种有效和高效的逆向工程过程。本文概述了当前的进程，并详细介绍了一种用于获取和合成大面积图像以及提取版图的新工具。将首次将生成的布局与已知绘制的GDS之间的误差作为品质因数(FOM)进行定量比较。从该布局中将提取ECC加密和电路块中的划分的电路图。
In view of potential risks of piracy and malicious manipulation of complex integrated circuits built in technologies of 45 nm and less, there is an increasing need for an effective and efficient process of reverse engineering. This paper provides an overview of the current process and details on a new tool for the acquisition and synthesis of large area images and the extraction of a layout. For the first time the error between the generated layout and the known drawn GDS will be compared quantitatively as a figure of merit (FOM). From this layout a circuit graph of an ECC encryption and the partitioning in circuit blocks will be extracted.