SIS : A System for Sequential Circuit Synthesis
SIS : A System for Sequential Circuit Synthesis
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发表时间：
1992
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通讯作者：
E. Sentovich;K. J. Singh;L. Lavagno;C. Moon;R. Murgai;A. Saldanha;H. Savoj;P. R. Stephan;R. Brayto
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作者：
E. Sentovich;K. J. Singh;L. Lavagno;C. Moon;R. Murgai;A. Saldanha;H. Savoj;P. R. Stephan;R. Brayto
SIS是一个交互式的时序电路综合和优化工具。给定状态转换表、信号转换图或时序电路的逻辑级描述，它在目标技术中产生优化的网表，同时保留时序输入输出行为。许多不同的程序和算法已集成到SIS中，允许用户在过程的每个阶段选择各种技术。它建立在MISII [5]之上，包括所有（组合）优化技术以及许多增强功能。SIS作为一个框架，在其中可以测试和比较各种算法，并作为自动合成和优化时序电路的工具。本文对SIS进行了概述。第一部分包含输入规范，STG（状态转换图）操纵，新的逻辑优化和验证算法，ASTG（异步信号转换图）操纵，PGA的（可编程门阵列）和综合的描述。第二部分包含一个教程示例，说明使用SIS的设计过程。
SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII [5] and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGA’s (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS.