Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN Circuits
Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN Circuits
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DOI：
10.1109/mcsoc.2019.00016
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发表时间：
2019-10
期刊：
影响因子：
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通讯作者：
Hayato Kato;H. Saito
中科院分区：
文献类型：
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作者：
Hayato Kato;H. Saito
为了提高性能，卷积神经网络 (CNN) 经常用于现场可编程门阵列 (FPGA)。在本文中，为了降低CNN电路的功耗，我们提出了一种在商用FPGA上设计异步CNN电路的设计方法。首先，所提出的方法将同步CNN电路的寄存器传输级（RTL）模型转换为异步CNN电路的RTL模型。然后，该方法使用商业 FPGA 设计环境设计异步 CNN 电路。在实验中，我们设计了异步CNN电路并评估了性能。与同步对应物相比，异步 CNN 电路消耗的能量大约减少了 2.3%。
To accelerate performance, Convolutional Neural Networks (CNNs) are frequently used in Field Programmable Gate Arrays (FPGAs). In this paper, to reduce the power consumption of CNN circuits, we propose a design method to design asynchronous CNN circuits on commercial FPGAs. First, the proposed method converts Register Transfer Level (RTL) models of synchronous CNN circuits to RTL models of asynchronous CNN circuits. Then, the proposed method designs asynchronous CNN circuits using a commercial FPGA design environment. In the experiment, we designed an asynchronous CNN circuit and evaluated the performance. Compared to the synchronous counterpart, the asynchronous CNN circuit consumed about 2.3% less energy.