A novel switch architecture for high-performance computing and signal processing networks
A novel switch architecture for high-performance computing and signal processing networks
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用于高性能计算和信号处理网络的新型交换机架构
DOI：
10.1109/nca.2004.1347780
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
W. Rosen
中科院分区：
文献类型：
--
作者：
Satyen Sukhtankar;D. Hecht;W. Rosen
这项工作描述了高性能分组交换网络的低延迟交换机架构。交换机架构是能够避免线头阻塞的输入缓冲器和能够允许不同输入端口同时访问单个输出端口的内部交换机互连的组合。该交换机专为RapidIO协议而设计，但在其他交换结构中也提供了更好的性能。OPNET Modeler被用来开发所提出的交换机架构的模型，并评估三种不同的网络拓扑结构的交换机的性能。两个标准的交换机架构的模型也被开发和仿真进行比较。
This work describes low-latency switch architecture for high performance packet-switched networks. The switch architecture is a combination of input buffers capable of avoiding head-of-line blocking and an internal switch interconnect capable of allowing different input ports to access a single output port simultaneously. The switch was designed for the RapidIO protocol, but provides improved performance in other switched fabrics as well. OPNET Modeler was used to develop models of the proposed switch architecture and to evaluate the performance of the switch for three different network topologies. Models of two standard switch architectures were also developed and simulated for comparison.