Loss modeling and optimization for monolithic implementation of the three-level buck converter
Loss modeling and optimization for monolithic implementation of the three-level buck converter
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三电平降压转换器单片实现的损耗建模和优化
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
D. Maksimović
中科院分区：
文献类型：
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作者：
Beomseok Choi;D. Maksimović
本文提出了基于参数提取的损耗建模，以减少针对单片实现优化的三电平降压转换器的高阶设计空间。提出了从模拟提取的参数导出的损失模型，以降低模型复杂性，同时保持准确的损失预测。通过转换器特性分析进一步缩小了设计空间。采用优化方法来选择电感器、开关频率以及功率器件和栅极驱动级的尺寸。通过 0.18 μm CMOS 工艺中的详细电路仿真，针对 3.7 至 1.15 V、4 MHz、2 A 转换器的损耗模型和优化方法进行了验证。
This paper presents parameter extraction based loss modeling to reduce the high-order design space for the three-level buck converter optimized for monolithic implementation. Loss models derived from simulation extracted parameters are presented to reduce model complexity while maintaining accurate loss predictions. The design space is reduced further by analysis of converter characteristics. An optimization approach is applied to select the inductor, the switching frequency, and the sizes of the power devices and the gate drive stages. The loss model and the optimization approach are validated for a 3.7-to-1.15 V, 4 MHz, 2 A converter through detailed circuit simulations in a 0.18 μm CMOS process.