Approximate Logic Synthesis: A Survey
Approximate Logic Synthesis: A Survey
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近似逻辑综合：综述
DOI：
10.1109/jproc.2020.3014430
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发表时间：
2020-12-01
影响因子：
20.6
通讯作者：
Reda, Sherief
中科院分区：
文献类型：
--
作者：
Scarabottolo, Ilaria;Ansaloni, Giovanni;Reda, Sherief
近似计算是一种新兴的范式，通过放松对完全精度的要求，在设计面积和功耗方面提供了好处。这种范式在底层计算对小错误具有固有弹性的应用程序中特别有吸引力。这样的应用在许多领域都很丰富，包括机器学习、计算机视觉和信号处理。在电路设计中，一个主要的挑战是自动合成近似电路的能力，而不依赖于设计师的专业知识。在这项工作中，我们回顾了设计来合成近似电路的方法，给出了它们的确切功能和近似阈值。我们总结了评估电路简化可能对输出产生的误差的策略，这指导综合技术在给定诱导误差的情况下选择导致最大收益的电路变换。然后，我们回顾了在门电平或布尔电平操作的电路简化方法，包括那些利用经典布尔合成技术来实现近似的方法。我们还总结了采用高级描述的策略，如C或行为Verilog，并从这些描述中合成近似电路。
Approximate computing is an emerging paradigm that, by relaxing the requirement for full accuracy, offers benefits in terms of design area and power consumption. This paradigm is particularly attractive in applications where the underlying computation has inherent resilience to small errors. Such applications are abundant in many domains, including machine learning, computer vision, and signal processing. In circuit design, a major challenge is the capability to synthesize the approximate circuits automatically without manually relying on the expertise of designers. In this work, we review methods devised to synthesize approximate circuits, given their exact functionality and an approximability threshold. We summarize strategies for evaluating the error that circuit simplification can induce on the output, which guides synthesis techniques in choosing the circuit transformations that lead to the largest benefit for a given amount of induced error. We then review circuit simplification methods that operate at the gate or Boolean level, including those that leverage classical Boolean synthesis techniques to realize the approximations. We also summarize strategies that take high-level descriptions, such as C or behavioral Verilog, and synthesize approximate circuits from these descriptions.