A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell
A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell
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基于 6T 混合 TFET-FinFET 单元的 125mV 2ns 访问时间 16Kb SRAM 设计
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
M. Pedram
中科院分区：
文献类型：
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作者：
H. Afzali;A. Shafaei;M. Pedram
本文提出了一种稳健且节能的混合 TFET-FinFET 6T SRAM 单元，该单元利用 TFET 比 FinFET 更高的开/关电流比，在超低电源电压下可靠地保存和访问数据。更准确地说，在所提出的混合单元中，为了实现低静态电流和高噪声容限，TFET 用于交叉耦合反相器，并且为了加快存取时间，高性能 FinFET 用于存取晶体管。该论文还提出了一种双 Vt 6T SRAM，其中低功耗（高 Vt）和高性能（低 Vt）FinFET 分别用于交叉耦合反相器和存取晶体管。对于两个 SRAM 单元，均采用 Vdd 升压读取辅助技术来提高读取稳定性。针对 128×128 SRAM 阵列的栅极长度为 20 nm 的技术，使用 HSPICE 仿真分析了这两种 SRAM 的特性。仿真结果表明，双 Vt 电池的最低工作 Vdd 为 225 mV，而混合电池的最低工作 Vdd 为 125 mV。此外，为了进一步降低混合单元的访问延迟（125 mV ≤ Vdd ≤ 225 mV），使用了负 Gnd 读取辅助技术和行解码器的升压电压。最后，本文提出了基于所提出的混合 TFET-FinFET SRAM 单元的 125mV 2ns 访问时间 16Kb SRAM 阵列。
This paper proposes a robust and energy-efficient hybrid TFET-FinFET 6T SRAM cell which takes advantage of the higher ON/OFF current ratio of TFETs compared to that of FinFETs to reliably hold and access data at ultra-low supply voltages. More precisely, in the proposed hybrid cell, to achieve low static currents along with high noise margins, TFETs are used for cross-coupled inverters, and to speed up the access time, high-performance FinFETs are utilized for access transistors. The paper also presents a dual-Vt 6T SRAM, in which low-power (high-Vt) and high-performance (low-Vt) FinFETs are used for cross-coupled inverters and access transistors, respectively. For both SRAM cells, the Vdd boost read-assist technique is employed to improve the read stability. Characteristics of both SRAMs are analyzed using HSPICE simulations for technologies with the gate length of 20 nm for a 128\times 128 SRAM array. Simulation results reveal that the lowest operating Vdd for the dual-Vt cell is 225 mV, whereas that of the hybrid cell is 125 mV. Moreover, to further decrease the access delay of the hybrid cell for 125 mV ≤ Vdd ≤ 225 mV, negative Gnd read-assist technique and a boosted voltage for the row decoder are used. Finally, the paper presents a 125mV 2ns-access-time 16Kb SRAM array based on the proposed hybrid TFET-FinFET SRAM cell.