Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs
复制标题
适用于混合信号 SOC 设计的快速基板噪声感知布局规划
DOI：
10.1109/tvlsi.2008.2001734
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发表时间：
2008
影响因子：
2.8
通讯作者：
D. Pan
中科院分区：
文献类型：
--
作者：
Minsik Cho;D. Pan
提出了一种基于块偏好有向图(BPDG)的混合信号片上系统(SOC)版图早期布局中基板噪声估计的新方法。在给定一组模拟和数字块的基础上，基于它们的固有噪声特性来构建BPDG，以捕获用于最小化衬底噪声的首选相对位置。对于序列对或B*树中的布局规划的每个实例，我们有效地统计了违反BPDG的数量，这与精确但计算密集型的衬底噪声建模具有很好的相关性。因此，我们的基于BPDG的模型可以指导混合信号SOC的快速衬底噪声感知版图规划和版图优化。实验结果表明，该方法比传统的基于全熔断衬底模型的布图规划方法有明显的提高。
In this paper, we introduce a novel substrate noise estimation technique during early floorplanning for mixed signal system-on-chip (SOC), based on block preference directed graph (BPDG). Given a set of analog and digital blocks, BPDG is constructed based on their inherent noise characteristics to capture the preferred relative locations for substrate noise minimization. For each instance of floorplan in sequence pair or B*-tree, we efficiently count the number of violations against BPDG which correlates remarkably well with accurate but computation-intensive substrate noise modeling. Thus, our BPDG-based model can guide fast substrate noise-aware floorplanning and layout optimization for mixed signal SOC. Our experimental results show that the proposed approach is significantly faster than conventional full-blown substrate model-based floorplanning.