An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising
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基于 FPGA 的全流水线双边网格，用于实时图像去噪
DOI：
10.1109/fpl53798.2021.00035
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
Shinya Takamaeda-Yamazaki
中科院分区：
文献类型：
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作者：
Nobuho Hashimoto;Shinya Takamaeda-Yamazaki
双边滤波器（BF）由于能够在去噪的同时保持图像的边缘，在图像处理中得到了广泛的应用。它的缺点在于它是非线性的，并且其计算复杂度和硬件资源与其窗口大小成正比。到目前为止，已经提出了几种近似方法和硬件实现来解决这些问题。然而，在严重的硬件资源限制下真实的时间处理大规模和高分辨率图像仍然是一个挑战。本文提出了一种基于双边网格（BG）的实时图像去噪系统，使用FPGA。在BG中，由x轴和y轴组成的2D图像被投影到称为“网格”的3D空间上，该网格由与输入图像的x分量、y分量和强度值相关的轴组成。然后使用高斯滤波器使该网格模糊，并且通过对网格进行插值来生成输出图像。虽然可以在BF中改变窗口大小，但是不能在BG中的输入图像上改变窗口大小。这使得难以将BG与BF相关联，并且难以获得在窗口半径增大时抑制硬件资源增加的特性。这项研究表明，一个BG与一个可变大小的窗口可以实现通过引入窗口半径参数，其中窗口半径的网格上总是1。然后，我们在FPGA上实现这个BG在一个完全流水线的方式。此外，我们验证了我们的设计抑制了硬件资源的增加，即使当窗口大小被扩大，并优于现有的设计在计算速度和硬件资源方面。
The bilateral filter (BF) is widely used in image processing because it can perform denoising while preserving edges. It has disadvantages in that it is nonlinear, and its computational complexity and hardware resources are directly proportional to its window size. Thus far, several approximation methods and hardware implementations have been proposed to solve these problems. However, processing large-scale and high-resolution images in real time under severe hardware resource constraints remains a challenge. This paper proposes a real-time image denoising system that uses an FPGA based on the bilateral grid (BG). In the BG, a 2D image consisting of x- and y-axes is projected onto a 3D space called a “grid,” which consists of axes that correlate to the x-component, y-component, and intensity value of the input image. This grid is then blurred using the Gaussian filter, and the output image is generated by interpolating the grid. Although it is possible to change the window size in the BF, it is impossible to change it on the input image in the BG. This makes it difficult to associate the BG with the BF and to obtain the property of suppressing the increase in hardware resources when the window radius is enlarged. This study demonstrates that a BG with a variable-sized window can be realized by introducing the window radius parameter wherein the window radius on the grid is always 1. We then implement this BG on an FPGA in a fully pipelined manner. Further, we verify that our design suppresses the increase in hardware resources even when the window size is enlarged and outperforms the existing designs in terms of computation speed and hardware resources.