Implementation of Sparse Superposition Codes
Implementation of Sparse Superposition Codes
复制标题
稀疏叠加码的实现
DOI：
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发表时间：
2017
影响因子：
5.4
通讯作者：
W. Gross
中科院分区：
文献类型：
--
作者：
C. Condo;W. Gross
稀疏叠加码是一种容量实现码，其译码过程是一个线性感知问题。因此，解码方法利用近似消息传递算法，该算法已被证明在压缩感知方面是有效的。作者之前的工作已经评估了有限精度和有限码长下ssc的纠错性能。本文提出了文献中第一个SSC编码器和解码器架构。这些架构是参数化的，适用于所有ssc：然后考虑一系列广泛的案例研究，然后提供特定于代码的近似，以及65纳米CMOS技术的实现结果。编码过程功耗低（<inline-formula> < text -math符号="LaTeX">$leq ext{2.103}$</ text -math></inline-formula> mW），半并行解码器架构采用<inline-formula>< text -math符号="LaTeX">$768乘以6$ </ text -math></inline-formula>-bit SSC码字，占地2.43 mm<inline-formula> < text -math符号="LaTeX">$^2$</ text -math></inline-formula>)，吞吐量可达1.3 Gb/s。
Sparse superposition codes (SSCs) are capacity achieving codes whose decoding process is a linear sensing problem. Decoding approaches thus exploit the approximate message passing algorithm, which has been proven to be effective in compressing sensing. Previous work from the authors has evaluated the error correction performance of SSCs under finite precision and finite code length. This paper proposes the first SSC encoder and decoder architectures in the literature. The architectures are parametrized and applicable to all SSCs: A set of wide-ranging case studies is then considered, and code-specific approximations, along with implementation results in 65 nm CMOS technology, are then provided. The encoding process can be carried out with low power consumption (<inline-formula> <tex-math notation="LaTeX">$leq ext{2.103}$</tex-math></inline-formula> mW), while the semi-parallel decoder architecture can reach a throughput of 1.3 Gb/s with a <inline-formula><tex-math notation="LaTeX">$768 imes 6$ </tex-math></inline-formula>-bit SSC codeword and an area occupation of 2.43 mm<inline-formula> <tex-math notation="LaTeX">$^2$</tex-math></inline-formula>.
影响因子：
2.5
作者：
Rush, Cynthia;Greig, Adam;Venkataramanan, Ramji
通讯作者：
Venkataramanan, Ramji