An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits
An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits
复制标题
一种高效、精确的设计方法，可优化失配和闪烁噪声敏感模拟电路中的器件区域
DOI：
10.1109/icecs.2001.957687
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
R. Thewes
中科院分区：
文献类型：
--
作者：
C. Paulus;R. Brederlow;U. Kleine;R. Thewes
提出了一种新的方法，使我们能够优化复杂的失配和1/f噪声敏感的模拟集成电路中的有源器件面积。该方法是基于一个完全的分析方法，并代表了一个有效的替代耗时的蒙特-卡罗模拟和数值迭代程序。此外，它还允许我们以高精度估计保证匹配和噪声性能所需的总芯片面积。该方法适用于混合信号电路设计流程中的集成。
A new method is presented which allows us to optimize active device area in complex mismatch- and 1/f-noise-sensitive analog integrated circuits. The method is based on a fully analytical approach and represents an efficient alternative to time consuming Monte-Carlo simulations and numerical iteration procedures. Moreover, it allows us to estimate total chip areas required to guarantee matching and noise performance with a high precision. The method is suitable for integration in the design flow of mixed signal circuits.