Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation
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DOI:
10.1587/transfun.e92.a.2979
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发表时间:
2009-12
期刊:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
影响因子:
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通讯作者:
Yuchun Ma;Xin Li;Yu Wang;Xianlong Hong
Yuchun Ma;Xin Li;Yu Wang;Xianlong Hong
中科院分区:
其他
文献类型:
--
作者:
Yuchun Ma;Xin Li;Yu Wang;Xianlong Hong

文献摘要

相似文献

在3D IC设计中,热问题是一个关键的挑战。为了消除热点,物理布局总是通过一些增量更改进行调整,例如移动或复制热块。在本文中,我们区分了三个不同类别的热感知增量变化:迁移计算,增长单元和移动热点块。然而,这些修改可能会大大降低封装面积以及互连分布。本文根据这些不同的增量变化,设计了混合整数线性规划(MILP)模型,使多个目标可以同时优化。此外,为了避免随机增量修改,这可能是低效的并且需要长的运行时间来收敛,这里针对每个候选增量改变对潜在增益进行建模。基于潜在增益,提出了一种新的热优化流程,智能地选择最佳的增量操作。实验结果表明,在MCNC/GSRC基准测试中,迁移计算、增长单元和移动热点分别使最大片内温度降低了7%、13%和15%。尽管如此,实验结果也表明,热优化流程可以减少14%的最大片上温度由现有的3D布图规划工具CBA产生的初始包装,并实现更好的面积和总的线长的改善比单独的操作。结果表明,在CBA_T(热感知CBA布局规划器)的初始填充下,我们的增量优化流程可以获得13.5%的温度降低。
In 3D IC design, thermal issue is a critical challenge. To eliminate hotspots, physical layouts are always adjusted by some incremental changes, such as shifting or duplicating hot blocks. In this paper, we distinguish the thermal-aware incremental changes in three different categories: migrating computation, growing unit and moving hotspot blocks. However, these modifications may degrade the packing area as well as interconnect distribution greatly. In this paper, mixed integer linear programming (MILP) models are devised according to these different incremental changes so that multiple objectives can be optimized simultaneously. Furthermore, to avoid random incremental modification, which may be inefficient and need long runtime to converge, here potential gain is modeled for each candidate incremental change. Based on the potential gain, a novel thermal optimization flow to intelligently choose the best incremental operation is presented. Experimental results show that migrating computation, growing unit and moving hotspot can reduce max on-chip temperature by 7%, 13% and 15% respectively on MCNC/GSRC benchmarks. Still, experimental results also show that the thermal optimization flow can reduce max on-chip temperature by 14% to the initial packings generated by an existing 3D floorplanning tool CBA, and achieve better area and total wirelength improvement than individual operations do. The results with the initial packings from CBA_T (Thermal-aware CBA floorplanner) show that 13.5% temperature reduction can be obtained by our incremental optimization flow.