Deep Learning on FPGAs with Multiple Service Levels for Edge Computing
Deep Learning on FPGAs with Multiple Service Levels for Edge Computing
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DOI：
10.1109/icac55051.2022.9911081
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发表时间：
2022-09
期刊：
影响因子：
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通讯作者：
Cong Gao;S. Saha;Yufan Lu;Rappy Saha;K. Mcdonald-Maier;X. Zhai
中科院分区：
文献类型：
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作者：
Cong Gao;S. Saha;Yufan Lu;Rappy Saha;K. Mcdonald-Maier;X. Zhai
在物联网时代（IoT）时代，深度学习是一种从物联网设备中提取信息的承诺方法。在最近的研究中提出了加速器，以加快此类DNN的执行。对这种实施的巨大挑战。本文我们提出了一个基于整数线性编程的最佳解决方案策略，以选择服务级别，以最大程度地提高特定资源的总体概念案例研究。还提供了物理FPGA。
In the Internet of Things (IoT) era, deep learning is emerging as a promising approach for extracting information from IoT devices. Deep learning is also employed in the edge computing environment based on the demand for faster processing. In the edge server, various hardware accelerators have been proposed in recent studies to speed up the execution of such DNNs. One such accelerator is Xilinx’s Deep Learning Processor Unit (DPU), designed for FPGA-based systems. However, the limited resource capacity of FPGAs in these edge servers imposes an enormous challenge for such implementation. Recent research has shown a clear trade-off between the “resources consumed” vs. the “performance achieved Taking a cue from these findings, we address the problem of efficient implementation of deep learning into the edge computing environment in this paper. The edge server employs FPGAs for executing the deep learning model. Each deep learning network is equipped with multiple distinct implementations represented by different service levels based on resource usage (where a higher service level implies higher performance with high resource consumption). To this end, we propose an Integer Linear Programming based optimal solution strategy for selecting a service level to maximize the overall performance subject to a given resource bound. Proof-of-concept case study with a deep learning network of multiple service levels of DPUs on a physical FPGA has also been provided.