CGRA-ME: A unified framework for CGRA modelling and exploration
CGRA-ME: A unified framework for CGRA modelling and exploration
复制标题
CGRA-ME：CGRA 建模和探索的统一框架
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
J. Anderson
中科院分区：
文献类型：
--
作者：
S. Alexander Chin;N. Sakamoto;A. Rui;Jim Zhao;Jin Hee Kim;Yuko Hara;J. Anderson
粗颗粒可重新配置阵列（CGRA）是一种可编程逻辑设备的样式，位于FPGA和自定义ASIC之间，可编程性，性能，功率和成本。学术界和工业都提出了CGRA；但是，先前的工作主要是独立的，没有广泛的建筑探索和与竞争性的CGRA进行比较。我们提出CGRA -ME-一个统一的CGRA框架，其中包含通用体系结构说明，体系结构建模，应用程序映射和物理实现。在此框架内，我们讨论了我们的体系结构说明语言CGRA-ADL，基于LLVM的一般模拟退火映射器以及用于物理实现的标准单元流。提出了一个体系结构探索案例研究，通过探索各种功能，互连，阵列大小和执行环境，通过映射应用程序基准和标准单元设计的生产来突出显示CGRA-ME的功能。
Coarse-grained reconfigurable arrays (CGRAs) are a style of programmable logic device situated between FPGAs and custom ASICs on the spectrum of programmability, performance, power and cost. CGRAs have been proposed by both academia and industry; however, prior works have been mainly self-contained without broad architectural exploration and comparisons with competing CGRAs. We present CGRA-ME - a unified CGRA framework that encompasses generic architecture description, architecture modelling, application mapping, and physical implementation. Within this framework, we discuss our architecture description language CGRA-ADL, a generic LLVM-based simulated annealing mapper, and a standard cell flow for physical implementation. An architecture exploration case study is presented, highlighting the capabilities of CGRA-ME by exploring a variety of architectures with varying functionality, interconnect, array size, and execution contexts through the mapping of application benchmarks and the production of standard cell designs.