10-kV, 123-mOcm2 4H-SiC power DMOSFETs
10-kV, 123-mOcm2 4H-SiC power DMOSFETs
复制标题
DOI：
--
复制
发表时间：
2004-08
影响因子：
4.9
通讯作者：
S. Ryu;S. Krishnaswami;M. O'loughlin;J. Richmond;A. Agarwal;J. Palmour;A. Hefner
中科院分区：
文献类型：
--
作者：
S. Ryu;S. Krishnaswami;M. O'loughlin;J. Richmond;A. Agarwal;J. Palmour;A. Hefner
KV，123m cm功率DMOSFET在4H-SIC中得到了验证。与先前报道的值相比，通过使用85米厚的Cm掺杂的漂移外延层，实现了42%的降低。从测试的MOSFET上测得有效沟道迁移率为22 cm/vs。在栅极偏置为18V时，测得比导通电阻为123m cm，相当于aN为3 mV/cm。在漏极偏压为10kV时，测得有效面积为cm的4H-SiC型DMOSFET的漏电流为197A。在4.6kV、1.3A的开关测量中测得开关时间为100 ns。这表明4H-SIC功率DMOSFET是高压、高速开关应用的理想选择。植入物激活率和磁场氧化层电荷的变化。本文报道的器件采用了具有多个浮动保护环的边缘终端结构，对这些问题不太敏感。该器件使用了50个保护环，终止结构的长度为400m，在650℃左右通过铝注入形成表面浓度为cm，深度为0.4m的峰值浓度为cm的逆行p势垒，然后通过大剂量氮离子注入形成n源区。MOS栅长由p井和n源注入体之间的距离决定，为1.5m，掩模设计的栅填充密度为426 cm/cm。JFET间隙由两个相邻的p-势垒之间的距离定义，为5米。JFET区域被注入氮离子，掺杂浓度为厘米
kV, 123 m cm Power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in , compared to a previ- ously reported value, was achieved by using an cm doped, 85- m-thick drift epilayer. An effective channel mobility of 22 cm /Vs was measured from a test MOSFET. A specific on-re- sistance of 123 m cm were measured with a gate bias of 18 V, which corresponds to an of 3 MV/cm. A leakage current of 197 A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of cm . A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measure- ments. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications. variations in implant activation rate and field oxide charges. The device reported in this paper used an edge termination struc- ture with multiple floating guard rings, which is less sensitive to those problems. Fifty guard rings were used in this device, and the length of the termination structure is 400 m. Retrograde p-wells, with a surface concentration of cm and a peak concentration of cm at a depth of 0.4 m, were formed by aluminum implantation at around 650 C, and the n source regions were then formed by a heavy dose nitrogen implantation. The MOS gate length, determined by the distance between the p-well and the n source implants, is 1.5 m. The gate packing density for the mask design is 426 cm/cm . The JFET gap, defined by the distance between two adjacent p-wells, is 5 m. The JFET regions were implanted with nitrogen ions to a doping concentration of cm