Performance and reliability driven clock scheduling of sequential logic circuits
Performance and reliability driven clock scheduling of sequential logic circuits
复制标题
时序逻辑电路的性能和可靠性驱动时钟调度
DOI：
10.1109/aspdac.1997.600055
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
Y. Kajitani
中科院分区：
文献类型：
--
作者：
A. Takahashi;Y. Kajitani
众所周知，如果对每个寄存器的时钟到达时间加以控制，时序电路中的时钟周期可以短于寄存器之间的最大信号延迟。我们提出了一种求信号传播延迟给定电路的最小时钟周期的算法。在LGSynth93基准测试上的实验结果表明，与传统的基于最大信号延迟的方法相比，该技术可将时钟周期减少约16%。研究了该技术在提高电路可靠性方面的应用。
It is known that the clock-period in a sequential circuit can be shorter than the maximum signal delay between registers if the clock arrival time to each register is controlled. We propose an algorithm to find the minimum clock-period of a circuit whose signal propagation delays are given. Experimental results on LGSynth93 benchmarks show that this technique achieves as much as about 16% reduction of clock-period compared with the conventional maximum signal delay based methods. An application of this technique to improve the reliability of circuits is considered.