Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging
Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging
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DOI：
10.13154/tches.v2019.i3.86-118
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发表时间：
2019-05
期刊：
影响因子：
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通讯作者：
Bicky Shakya;Haoting Shen;M. Tehranipoor;Domenic Forte
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文献类型：
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作者：
Bicky Shakya;Haoting Shen;M. Tehranipoor;Domenic Forte
综合电路（IC）伪装已成为保护半导体知识产权（IP）免受反向工程的承诺解决方案。不幸的是，这种方法会导致高面积，延迟和动力开销，并且很容易受到侵入性，以及基于布尔斯满意度/VLSI测试的非侵入性攻击。细胞伪装策略被称为“掩盖门”，利用掺杂和虚拟触点创建伪装的细胞，这些细胞与现代成像技术下的常规标准单元无法区分。 SAT和基于测试的攻击在非常低的开销中。
Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. Existing methods of camouflaging are based on standard cells that can assume one of many Boolean functions, either through variation of transistor threshold voltage or contact configurations. Unfortunately, such methods lead to high area, delay and power overheads, and are vulnerable to invasive as well as non-invasive attacks based on Boolean satisfiability/VLSI testing. In this paper, we propose, fabricate, and demonstrate a new cell camouflaging strategy, termed as ‘covert gate’ that leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. We perform a comprehensive security analysis of covert gate, and show that it achieves high resiliency against SAT and test-based attacks at very low overheads. We also derive models to characterize the covert cells, and develop measures to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.