Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology
Design of a 2–12-GHz Bidirectional Distributed Amplifier in a 0.18- $\mu$ m CMOS Technology
复制标题
采用 0.18- $mu$ m CMOS 技术的 2–12 GHz 双向分布式放大器的设计
DOI：
10.1109/tmtt.2018.2883956
复制
发表时间：
2019
影响因子：
4.3
通讯作者：
A. Medi
中科院分区：
文献类型：
--
作者：
A. Alizadeh;M. Meghdadi;Majid Yaghoobi;A. Medi
本文提出了一种基于0.18-<inline-formula> < text -math符号="LaTeX">$\boldsymbol \mu \text{m}$ </ text -math></inline-formula> CMOS工艺的双向分布式放大器（BDDA）的设计与实现。对BDDA的性能进行了理论分析，给出了最佳增益级数（<inline-formula> < text -math notation="LaTeX">$n_{\text {opt}}$ </ text -math></inline-formula>）、最大可实现功率增益（<inline-formula> < text -math notation="LaTeX">$G_{P}$ </ text -math></inline-formula>）和电路带宽。此外，在考虑电路直流功耗（<inline-formula> < text -math notation="LaTeX">$n$ </ text -math></inline-formula> $P_{\text {dc}}$ </ text -math></inline-formula>）的情况下，给出了合理选择DA级数的新公式（即<inline-formula> < text -math notation="LaTeX">$n$ </ text -math notation="LaTeX">）。该公式优化了<inline-formula> < text -math符号="LaTeX">$G_{P}/P_{\text {dc}}$ </ text -math></inline-formula>，优于传统的<inline-formula> < text -math符号="LaTeX">$n_{\text {opt}}$ </ text -math></inline-formula>公式。为了验证理论分析，制作了一个2- 12 ghz BDDA，高输出1-dB压缩点为+16 dBm，小信号增益为10 dB。BDDA芯片占用1.89 mm<sup>2</sup>芯片面积，其平均测量噪声系数<inline-formula> < text -math notation="LaTeX">$P_{\text {dc}}$ </ text -math></inline-formula>在大功率模式下分别为6.8 dB和0.38 W和6.5 dB和0.13 W。
This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\boldsymbol \mu \text{m}$ </tex-math></inline-formula> CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages (<inline-formula> <tex-math notation="LaTeX">$n_{\text {opt}}$ </tex-math></inline-formula>), maximum achievable power gain (<inline-formula> <tex-math notation="LaTeX">$G_{P}$ </tex-math></inline-formula>), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., <inline-formula> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula>) is offered where dc-power consumption of the circuit (<inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}}$ </tex-math></inline-formula>) is also considered. This formula optimizes <inline-formula> <tex-math notation="LaTeX">$G_{P}/P_{\text {dc}}$ </tex-math></inline-formula>, and it is preferred over the conventional <inline-formula> <tex-math notation="LaTeX">$n_{\text {opt}}$ </tex-math></inline-formula> formula. To validate the theoretical analyses, a 2–12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm<sup>2</sup> die area, and its average measured noise figure and <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}}$ </tex-math></inline-formula> are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively.