A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection

A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection
复制标题

具有传感器内电流域三元加权 MAC 运算的 0.2 至 3.6TOPS/W 可编程卷积成像器 SoC,用于特征提取和感兴趣区域检测

DOI:
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发表时间:
2021
期刊:
IEEE International Solid-State Circuits Conference
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通讯作者:
D. Bol
D. Bol
中科院分区:
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文献类型:
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作者:
M. Lefebvre;Ludovic Moreau;R. Dekimpe;D. Bol

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混合信号视觉芯片在智能手机、可穿戴设备和物联网节点上的低功耗嵌入式计算机视觉应用中变得越来越受欢迎,因为它们满足严格的功耗和面积限制,同时为中低级别图像处理任务保持足够的精度。一方面,传感器内处理 [1, 2] 支持大规模并行操作,但依赖于像素级处理元件,这些元件会降低像素间距并将卷积感受野限制为相邻像素 [1],从而排除多尺度操作。另一方面,近传感器处理 [3-5] 可以通过像素下采样 [3] 或合并 [4] 在多个尺度上运行,但需要大量的功耗和面积开销,因为需要模拟存储器来存储等待处理的像素值。此外,以前的近传感器处理 SoC 通常是特定于应用的,因此通用性有限。在本文中,我们提出了一款代号为 SleepSpotter 的 65nm QQVGA 卷积成像器 SoC,能够基于传感器内当前域 MAC 操作进行多功能特征提取和感兴趣区域 (RoI) 检测。它以 6 种不同的尺度运行,具有可编程滤波器大小 (F)、步幅 (S) 和三元滤波器权重 (1.5b)。它的最低能量为 2.5pJ/像素·帧·滤波器,峰值效率为 3.6TOPS/W,实现卷积所需的像素面积开销为 29%,且无需模拟存储器。
Mixed-signal vision chips are becoming increasingly popular for low-power embedded computer vision applications on smartphones, wearables and IoT nodes, as they meet stringent power and area constraints while maintaining a sufficient level of accuracy for low- to medium-level image processing tasks. On the one hand, in-sensor processing [1, 2] enables massively parallel operation but relies on pixel-level processing elements that degrade the pixel pitch and restrict the convolutional receptive field to neighboring pixels [1], precluding multi-scale operation. On the other hand, near-sensor processing [3–5] can operate at multiple scales by pixel downsampling [3] or binning [4] but entails significant power and area overhead as an analog memory is required to store pixel values awaiting processing. In addition, previous near-sensor processing SoCs are generally application-specific and thus suffer from limited versatility. In this paper, we present a 65nm QQVGA convolutional imager SoC codenamed SleepSpotter capable of versatile feature extraction and region-of-interest (RoI) detection based on in-sensor current-domain MAC operations. It operates at 6 different scales, features programmable filter size (F), stride (S), and ternary filter weights (1.5b). It reaches a minimum energy of 2.5pJ/pixel•frame•filter and a peak efficiency of 3.6TOPS/W, with 29% pixel area overhead for enabling the convolution and without the need for an analog memory.