Characterization of an Associative Memory Chip in 28 nm CMOS Technology
Characterization of an Associative Memory Chip in 28 nm CMOS Technology
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采用 28 nm CMOS 技术的关联存储芯片的特性
DOI：
10.1109/iscas.2018.8351801
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
S. Viret
中科院分区：
文献类型：
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作者：
A. Annovi;G. Calderini;S. Capra;B. Checcucci;F. Crescioli;F. Canio;G. Fedi;L. Frontini;M. Garci;C. Gentsos;T. Kubota;V. Liberali;F. Palla;J. Shojaii;C. Sotiropoulou;A. Stabile;G. Traversi;S. Viret
本文介绍了采用 28 nm CMOS 设计和制造的新型关联内存芯片（版本 7）的特性。该设计旨在： 增强与 FPGA 之间的链接；得益于完全定制的 LVDS 收发器，增加了带宽；通过采用全定制方法设计的新存储单元来降低功耗和硅面积。 2016年12月提交设计；原型采用 17 × 17 球栅阵列 (BGA) 独立封装制造和封装。原型表征确认了芯片的功能。最终芯片将与裸露的 FPGA 芯片一起组装在系统级封装 (SiP) 中。
This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.