Design rules for paralleling of Silicon Carbide Power MOSFETs
Design rules for paralleling of Silicon Carbide Power MOSFETs
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碳化硅功率 MOSFET 并联设计规则
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
Stradale Primosole
中科院分区：
文献类型：
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作者：
S. Mantia;Stradale Primosole
通过使用多个并联的单独 MOSFET 来提高功率开关的能力是硅半导体器件的常见做法。本文介绍了与碳化硅 (SiC) MOSFET 并联相关问题的调查结果。基于并联分立器件的实验验证，研究重点是影响并联开关性能的主要电气参数。此外，还研究了电路失配对并联 SiC MOSFET 的影响，以及为减轻不完全对称布局的影响而定制的“开尔文源”连接的影响。我们开发了一种专用测试车辆，将所有这些方面纳入评估，并对额定电流高达 300A 的开关元件进行测试。
Increasing the capability of a power switch by using several individual MOSFETs connected in parallel is a common practice with silicon semiconductor devices. This paper deals with the results of an investigation of the issues linked to paralleling the Silicon Carbide (SiC) MOSFETs. Based on the experimental validation of paralleled discrete devices the investigation focuses on the main electrical parameters affecting the performance of the paralleled switch. Moreover the influence of circuit mismatch on paralleling SiC MOSFETs is investigated as well as the impact of the “Kelvin source” connection that is tailored to mitigate the effects of not fully symmetric layout. A dedicated test vehicle has been developed to include all these aspects in the evaluation and carry out the tests on a switch element rated up to 300A.