Submicron 3D Surface-Orientation-Optimized CMOS Technology
Submicron 3D Surface-Orientation-Optimized CMOS Technology
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亚微米 3D 表面取向优化 CMOS 技术
DOI:
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发表时间:
1986
期刊:
影响因子:
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通讯作者:
J. Matsunaga
中科院分区:
文献类型:
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作者:
M. Kinugawa;M. Kakumu;J. Matsunaga
INTIODUCTION For achieving high performance VLSI's in logic and memory applications, CMOS becomes the dominant technology due to its high speed operation and low power dissipation. However, since (100) wafer is used from a view point of NMOSFET's characteristics, conventional planar technologies give rise to loss of balance between electron and hole mobility. This unbalance results in large PMOS device size for designing optimum circuits, which naturally increases parasitic capacitances such as junction capacitance and gate capacitance. As a result, obtained CMOS operation speed is lower than expected. (110) Si surface is thus more preferable for PMOSFET's due to the highest hole mobility. However, it degrades NMOS reliability, which is highest on (100) surface orientation [1]. Therefore, it is most desirable to utilize optimum Si surface orientation for NMOSFET's and PMOSFET's individually on the same substrate. In this paper, a 3-dimensional CMOS (3D CMOS) structure has been proposed. In this structure, PMOSFET's are fabricated on a (110) surface obtained by a trench sidewall formed on a (100) Si substrate, while NMOSFET's are fabricated on the (100) substrate as usual. Therefore, the highest hole mobility is obtained for PMOSFET's, maintaining high NMOS reliability. Based upon this technology, the 3D CMOS was fabricated and its device performance was characterized.