Submicron 3D Surface-Orientation-Optimized CMOS Technology

Submicron 3D Surface-Orientation-Optimized CMOS Technology
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亚微米 3D 表面取向优化 CMOS 技术

DOI:
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发表时间:
1986
期刊:
1986 Symposium on VLSI Technology. Digest of Technical Papers
影响因子:
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通讯作者:
J. Matsunaga
J. Matsunaga
中科院分区:
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文献类型:
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作者:
M. Kinugawa;M. Kakumu;J. Matsunaga

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为了实现高性能的超大规模集成电路的逻辑和存储器应用,CMOS成为占主导地位的技术,由于其高速操作和低功耗。然而,由于从NMOSFET的特性的观点来看使用(100)晶片,因此常规平面技术导致电子和空穴迁移率之间的平衡的丧失。这种不平衡导致用于设计最佳电路的大PMOS器件尺寸,这自然增加了诸如结电容和栅极电容的寄生电容。结果,获得的CMOS操作速度低于预期。(110)因此,Si表面由于最高的空穴迁移率而更优选用于PMOSFET。然而,它降低了NMOS的可靠性,其在(100)表面取向上最高[1]。因此,最理想的是在同一衬底上分别为NMOSFET和PMOSFET利用最佳的Si表面取向。提出了一种三维CMOS结构。在该结构中,PMOSFET被制造在通过在(100)Si衬底上形成的沟槽侧壁获得的(110)表面上,而NMOSFET通常被制造在(100)衬底上。因此,PMOSFET的空穴迁移率最高,保持高NMOS的可靠性。在此基础上,制作了3D CMOS,并对其器件性能进行了表征。
INTIODUCTION For achieving high performance VLSI's in logic and memory applications, CMOS becomes the dominant technology due to its high speed operation and low power dissipation. However, since (100) wafer is used from a view point of NMOSFET's characteristics, conventional planar technologies give rise to loss of balance between electron and hole mobility. This unbalance results in large PMOS device size for designing optimum circuits, which naturally increases parasitic capacitances such as junction capacitance and gate capacitance. As a result, obtained CMOS operation speed is lower than expected. (110) Si surface is thus more preferable for PMOSFET's due to the highest hole mobility. However, it degrades NMOS reliability, which is highest on (100) surface orientation [1]. Therefore, it is most desirable to utilize optimum Si surface orientation for NMOSFET's and PMOSFET's individually on the same substrate. In this paper, a 3-dimensional CMOS (3D CMOS) structure has been proposed. In this structure, PMOSFET's are fabricated on a (110) surface obtained by a trench sidewall formed on a (100) Si substrate, while NMOSFET's are fabricated on the (100) substrate as usual. Therefore, the highest hole mobility is obtained for PMOSFET's, maintaining high NMOS reliability. Based upon this technology, the 3D CMOS was fabricated and its device performance was characterized.