A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS
A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS
复制标题
采用 32nm CMOS 的可扩展 3.6 至 5.2mW 5 至 10Gb/s 4 抽头 DFE
DOI：
10.1109/isscc.2009.4977367
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
F. Spagna
中科院分区：
文献类型：
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作者：
Lidong Chen;Xuguang Zhang;F. Spagna
芯片和模块之间的宽带通信依靠大量高速串行IO实现。在这种情况下，最关键的问题是克服互连符号间干扰（ISI），同时保持低功耗和高能效的功率可扩展的紧凑型判决反馈均衡（DFE）显然适合这种设计空间的需求。在具有电阻负载的差分CML电路中实现的DFE中，最高数据速率由CML求和器输出处的RC时间常数和判决反馈必须在1UI内建立的时序约束确定。这样的结构不是功率可扩展的，并且精密无源电阻器的要求增加了诸如32 nm的精细特征工艺的成本。最近提出了一种电流积分DFE加法器，以消除电阻性负载并减轻建立时间限制[1，2]。本文提出了一种功率可扩展的5至10 Gb/s 4抽头DFE，通过使用三种电路技术提供进一步的功耗节省：1：2解复用电流积分求和器，检测放大器（SA）锁存判决反馈，和全差分电流回收DAC（I-DAC）。
Wide bandwidth communication between chips and modules has been achieved relying on large numbers of high-speed serial IOs. In this context, the most critical issue is overcoming the interconnect inter-symbol interference (ISI) while keeping low power dissipation and an energy-efficient power-scalable compact decision-feedback equalization (DFE) clearly fits the needs of this design space. In DFEs implemented in differential CML circuits with resistive load, the highest data rate is determined by the RC time constant at the CML summer output and the timing constraint that decision feedback must be settled within 1UI. Such a structure is not power scalable, and the requirement of precision passive resistor adds cost to such fine-feature process as 32nm. A current-integrating DFE summer was recently presented to eliminate resistive load and mitigate settling time constraint [1,2]. This paper presents a power-scalable 5-to-10Gb/s 4-tap DFE that provides further power savings by using three circuit techniques: 1:2 demultiplexed current-integrating summer, sense-amplifier (SA) latched-decision feedback, and fully differential current-recycled DACs (I-DACs).