ATPG-based cost-effective, secure logic locking
ATPG-based cost-effective, secure logic locking
复制标题
基于ATPG的经济有效的安全逻辑锁定
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
O. Sinanoglu
中科院分区：
文献类型：
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作者：
A. Sengupta;M. Nabeel;Muhammad Yasin;O. Sinanoglu
IC供应链的全球化导致了硬件安全威胁的出现，例如IP盗版，逆向工程，过度建筑物和硬件特洛伊木马。最新的锁定技术SFLL阻碍了可证明且可量化的安全性的所有最新攻击，包括SAT，APPSAT和删除攻击，但是有时可以禁止SFLL的实施成本，因为它缺乏自动框架。这探讨了本文的成本效益实施方案，我们可以将VLSI测试原理和工具用于自动化SFLL的关键步骤并最小化其成本。设计选择和ATPG评估我们的实验结果。
The globalization of IC supply chain lead to the emergence of hardware security threats such as IP piracy, reverse engineering, overbuilding, and hardware Trojans. Among the techniques developed to mitigate these threats, logic locking offers the most versatile protection and is being actively researched. The most recent locking technique SFLL thwarts with provable and quantifiable security all the state-of-the-art attacks including SAT, AppSAT, and the removal attack. However, the implementation cost of SFLL can sometimes be prohibitive, as it lacks an automated framework that explores cost-effective implementation options. In this paper, we show how VLSI testing principles and tools can be adopted to automate critical steps in SFLL and minimize its cost. We propose “SFLL-fault” that utilizes fault injection driven synthesis to efficiently explore design options and ATPG to assess security levels. Our experimental results confirm the efficacy of our strategy; SFLL-fault can reduce the implementation cost by 35% compared to SFLL without compromising security.