High-level synthesis of accelerators in embedded scalable platforms
High-level synthesis of accelerators in embedded scalable platforms
复制标题
嵌入式可扩展平台中加速器的高级综合
DOI：
10.1109/aspdac.2016.7428012
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
L. Carloni
中科院分区：
文献类型：
--
作者：
Paolo Mantovani;G. D. Guglielmo;L. Carloni
嵌入式可扩展平台联合收割机结合了用于异构片上系统（SoC）设计的灵活的套接字架构和配套的系统级设计方法。该架构支持处理器内核与许多专用硬件加速器的快速集成。该方法简化了SoC中异构组件的设计、集成和编程，提高了设计过程的抽象层次，指导设计人员应用高级综合（HLS）工具。HLS使加速器的设计更加高效，专注于其算法属性，更广泛地探索其设计空间，并在许多不同的SoC项目中进行更有效的重用。
Embedded scalable platforms combine a flexible socketed architecture for heterogeneous system-on-chip (SoC) design and a companion system-level design methodology. The architecture supports the rapid integration of processor cores with many specialized hardware accelerators. The methodology simplifies the design, integration, and programming of the heterogeneous components in the SoC. In particular, it raises the level of abstraction in the design process and guides designers in the application of high-level synthesis (HLS) tools. HLS enables a more efficient design of accelerators with a focus on their algorithmic properties, a broader exploration of their design space, and a more productive reuse across many different SoC projects.