System-in-Package, a Combination of Challenges and Solutions
System-in-Package, a Combination of Challenges and Solutions
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系统级封装，挑战与解决方案的结合
DOI：
10.1109/ets.2007.40
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
M. Renovell
中科院分区：
文献类型：
--
作者：
P. Cauvet;S. Bernard;M. Renovell
系统级封装（SiP）近来已成为半导体工业中的重要技术，其在不增加整体形状因子的情况下向消费者应用提供许多新的产品特征。在这个演讲中，首先讨论了SiP的基本概念，展示了SiP和SoC之间的区别，并通过一些来自现实生活的例子来说明。具体的挑战被认为是从测试的角度来看，集中在组装的成品率和缺陷水平的封装SiP。各种裸芯片测试技术，以找到已知良好的芯片，包括其局限性，其次是两种技术，以测试在系统级的SiP：功能系统测试和嵌入式组件测试。对未来SiP设计和测试挑战的简要讨论结束了演讲。
System-in-package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.