Accelerating MPI Message Matching through FPGA Offload
Accelerating MPI Message Matching through FPGA Offload
复制标题
通过 FPGA 卸载加速 MPI 消息匹配
DOI：
10.1109/fpl.2018.00039
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
M. Herbordt
中科院分区：
文献类型：
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作者：
Qingqing Xiong;A. Skjellum;M. Herbordt
消息传递接口（MPI）是分布式内存高性能计算（HPC）系统的通信标准。由于 MPI 的处理要求，特别是通过遍历相应队列来匹配请求和消息，因此 HPC 中的超低延迟通信很难实现。许多研究人员通过重新设计队列或将队列卸载到硬件加速器来解决这一问题。然而，最先进的软件方法无法让 CPU "脱离苦海"，而硬件方法要么缺乏可扩展性，要么仍有很大的改进空间。随着大量紧密耦合的 CPU-FPGA 计算架构的出现，将 MPI 功能卸载到用户控制的硬件上现在变得可行；我们发现重新审视硬件方法很有成效。为了保持支持 MPI 所需的通用性，同时防止资源利用率过高，我们根据最近对 HPC 应用程序性能特点的分析，设计了 MPI 队列处理卸载。我们提出了一种新颖的两级消息队列设计：内容可寻址内存（CAM）与节省资源的硬件链接列表。我们还提出了一种优化方案，可在队列较长的情况下保持较高的速度。为了测试我们的设计，我们创建了一个基于 SOC 的测试平台，其中包括软核处理器和 MPI 通信栈的硬件实现。即使只使用了一小部分 Stratix-V 逻辑，我们的设计也能比两个著名的硬件设计快一到两个数量级。
The Message Passing Interface (MPI) is the {\it de facto} communication standard for distributed-memory High-Performance Computing (HPC) systems. Ultra-low latency communication in HPC is difficult to achieve because of MPI processing requirements, in particular matching requests and messages done by traversing the corresponding queues. Many researchers have addressed this issue by redesigning queues or by offloading them to hardware accelerators. However, state-of-art software approaches cannot free CPUs "from the misery'' and hardware approaches either lack scalability or still leave substantial room for further improvement. With the emergence of numerous tightly coupled CPU-FPGA computing architectures, offload of MPI functionality to user-controlled hardware is now becoming viable; we find it productive to revisit hardware approaches. To maintain the generality necessary to support MPI while preventing high resource utilization, we design our MPI queue processing offload based on a recent analysis of performance characteristics in HPC applications. We propose a novel, two-level message queue design: a content addressable memory (CAM) coupled with a resource-saving hardware linked-list. We also propose an optimization that maintains high speed in the cases when the queue is long. To test our design, we create an SOC-based testbed consisting of softcore processors and hardware implementations of the MPI communication stacks. Even while using only a small fraction of the Stratix-V logic, our design can be one to two orders of magnitude faster than two well-known hardware designs.