Design and evaluation of dynamic access ordering hardware
Design and evaluation of dynamic access ordering hardware
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动态访问排序硬件的设计与评估
DOI：
10.1145/237578.237594
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发表时间：
1996
期刊：
影响因子：
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通讯作者：
J. Aylor
中科院分区：
文献类型：
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作者：
S. Mckee;Assaji Aluwihare;Benjamin H. Clark;R. Klenke;Trevor C. Landon;C. W. Oliver;M. H. Salinas;A. E. Szymkowiak;K. L. Wright;W. Wulf;J. Aylor
内存带宽正迅速成为许多应用程序的性能限制因素，特别是对于科学向量处理或多媒体压缩（解压缩）等流计算。虽然这些计算缺乏使缓存有效的时间局部性，但它们具有可预测的访问模式。由于大多数现代DRAM组件支持使其能够比其他更快地执行某些访问序列的模式，因此流访问的可预测性使其能够重新排序以获得更好的存储器性能。我们描述和评估流存储器控制器系统，它结合了编译时检测流与执行时选择的访问顺序和问题。该技术是实用的实现，使用现有的编译器技术，只需要少量的专用硬件。与我们的原型系统，我们已经观察到的性能提高了13倍以上的正常缓存。
Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes caches effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe and evaluate a Stream Memory Controller system that combines compile-time detection of streams with execution-time selection of the access order and issue. The technique is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. With our prototype system, we have observed performance improvements by factors of 13 over normal caching.