Robust Cache-Aware Quantum Processor Layout
Robust Cache-Aware Quantum Processor Layout
复制标题
DOI：
10.1109/srds51746.2020.00035
复制
发表时间：
2020-09
期刊：
影响因子：
--
通讯作者：
Travis LeCompte;Fang Qi;Lu Peng
中科院分区：
文献类型：
--
作者：
Travis LeCompte;Fang Qi;Lu Peng
量子计算已经成为计算机体系结构和信息理论中最大的当前研究领域之一。由于有可能淘汰大量基于因子分解的加密方法，地球仪的公司和政府正在竞相建造第一台大规模量子计算机。目前，大多数量子计算机都是噪声中间尺度量子（NISQ），使用相对较小的不可靠量子位集合。虽然存在纠错方法，但它们需要大量的辅助量子位来保护数据量子位，这对于当前的NISQ机器来说是不实用的。然而，根据道林-内文定律，超导芯片上可用的量子比特正以类似于摩尔定律的指数速度增长。展望更大规模的量子机，我们研究了一种方法，通过使用利用更简单的纠错码的量子缓存来增加实现纠错的量子机的可用量子比特密度。或者，这也允许设计可靠的系统，同时满足量子算法的性能和量子比特要求。我们修改Qiskit量子模拟库与缓存和研究区域大小和拓扑结构的交换特性的算法执行的影响。我们还提出了我们的结果，并讨论了每个算法的推荐拓扑结构。最后，我们提出了混合横向扩展模拟，以研究缓存对未来大规模机器的影响。与最差拓扑相比，默认中央缓存拓扑的最大性能提高了2.15倍，这创建了一个强大的缓存感知量子处理器布局。
Quantum computation has taken over as one of the largest current research areas in computer architecture and information theory. With the potential to make a large number of factorization-based encryption methods obsolete, companies and governments around the globe are racing to build the first large-scale quantum computer. Currently, most quantum computers are noisy intermediate-scale quantum (NISQ), using a relatively small collection of unreliable qubits. While error correction methods exist, they require a large number of ancilla qubits to protect the data qubits which is not practical for use on current NISQ machines. However, following the Dowling-Neven Law, available qubits on a superconducting chip are growing at an exponential rate similar to Moore’s Law. Looking toward larger scale quantum machines, we examine a method to increase usable qubit density of quantum machines implementing error correction by using quantum caches that utilize simpler error correction codes. Alternatively, this also allows for the design of reliable systems while meeting the performance and qubit requirements for quantum algorithms. We modify the Qiskit quantum simulation library to work with caches and investigate the effects of region size and topology on the swap characteristics of algorithm execution. We also present our results and discuss recommended topologies for each algorithm. Lastly, we present mix scale-out simulations to examine the impact of cache on future large-scale machines. The default central cache topology gains a maximum performance increase of 2.15 times compared to the worst topology, which creates a robust cache-aware quantum processor layout.