9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio
9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio
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9.4 A 28nm CMOS 数字分数 N PLL，具有 −245.5dB FOM 和用于 802.11abgn/ac 无线电的三倍频器
DOI：
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
Li Lin
中科院分区：
文献类型：
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作者：
Xiang Gao;Luns Tee;Wanghua Wu;Kun;Arvind Anumula Paramanandam;A. Jha;Norman Liu;E. Chan;Li Lin
WiFi 802.11ac 256-QAM模式的快速适应需要具有非常低的集成相位误差的射频时钟来提供良好的EVM性能。另一方面，为了更低的成本和更长的电池寿命，总是希望更小的面积和更低的功率。本文提出了一种适用于双频802.11abgn/ac无线电的28 nm CMOSLO设计，总体结构如图9.4.1所示。它通过低噪声集成XTAL振荡器、利用1)背景参考时钟倍增器占空比误差校正和量化噪声消除、2)非周期性DCO抖动和补偿以及基于自混频三倍频的偏置LO频率计划的小数N数字锁相环来解决上述挑战。该锁相环设计实现了0.36°积分相位误差或0.17ps rms抖动，而功耗为9.5 mW，导致FOM达到-245.5dBforfrac-N PLL的创纪录水平。
The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned challenges with a low-noise integrated XTAL oscillator, a fractional-N digital PLL utilizing 1) background reference clock-doubler duty-cycle error correction and quantization noise cancellation, 2) non-periodic DCO dithering and compensation, and an offset LO frequency plan based on a self-mixing frequency tripler. The PLL design achieves 0.36° integrated phase error or 0.17ps rms jitter while consuming 9.5mW, leading to a record FOM of -245.5dBforfrac-N PLLs.