Event-driven gate-level simulation with GP-GPUs
Event-driven gate-level simulation with GP-GPUs
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DOI：
10.1145/1629911.1630056
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发表时间：
2009-07
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影响因子：
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通讯作者：
Debapriya Chatterjee;A. Deorio;V. Bertacco
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作者：
Debapriya Chatterjee;A. Deorio;V. Bertacco
逻辑仿真是现代硬件开发工作中设计工具流程的关键组成部分。它被广泛使用，从高层描述到门级描述，以验证设计的多个方面，特别是功能的正确性。尽管开发公司在模拟任务上投入了大量资源，特别是在门级，但它仍然远未达到验证复杂现代设计所需的性能要求。在这项工作中，我们提出了第一个由并行通用图形处理器（GPGPU）加速的事件驱动逻辑模拟器。我们的模拟器利用门级事件驱动设计来利用大型硬件设计典型的低开关活动的优势。我们开发了用于电路网表划分的新颖算法，并针对高度并行 GPGPU 主机进行了优化。此外，我们的流程旨在从目标硬件平台中提取最佳仿真性能。我们发现我们的实验原型可以处理由数百万个门组成的大型工业规模设计，并且比当前的商业事件驱动模拟器平均加速 13 倍。
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely from high level descriptions down to gate level ones to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task, particularly at the gate level, it is still far from achieving the performance demands required to validate complex modern designs. In this work, we propose the first event driven logic simulator accelerated by a parallel, general purpose graphics processor (GPGPU). Our simulator leverages a gate level event driven design to exploit the benefits of the low switching activity that is typical of large hardware designs. We developed novel algorithms for circuit netlist partitioning and optimized for a highly parallel GPGPU host. Moreover, our flow is structured to extract the best simulation performance from the target hardware platform. We found that our experimental prototype could handle large, industrial scale designs comprised of millions of gates and deliver a 13x speedup on average over current commercial event driven simulators.