Deep sub-micron stud-via technology for superconductor VLSI circuits
Deep sub-micron stud-via technology for superconductor VLSI circuits
复制标题
用于超导体 VLSI 电路的深亚微米螺柱过孔技术
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
M. Gouker
中科院分区：
文献类型：
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作者：
S. K. Tolpygo;V. Bolkhovsky;T. Weir;L. Johnson;W. Oliver;M. Gouker
一种用于在200 mm晶片上具有8和10个超导层的超导超大规模集成（VLSI）电路的最小尺寸低至250 nm的完全平坦化的Nb基超导层间连接（通孔）的制造工艺已经被开发。代替单个Nb布线层，其利用Nb/Al/Nb三层用于每个布线层以形成Nb柱（螺柱），从而提供在三层的底层中蚀刻的布线与也沉积为Nb/Al/Nb三层的下一布线层之间的垂直连接。该技术通过相对于目前使用的超导层之间的蚀刻接触孔减小互连的面积并且通过使得能够使用堆叠通孔，使得超导数字电路的密度的显著增加成为可能。结果的制造和尺寸依赖的Nb螺柱的电性能的尺寸附近的分辨率限制的248 nm光刻。所制备的钉孔中的超导临界电流密度约为0.3A/μm2，接近Nb膜的破坏电流密度。
A fabrication process has been developed for fully planarized Nb-based superconducting inter-layer connections (vias) with minimum size down to 250 nm for superconductor very large scale integrated (VLSI) circuits with 8 and 10 superconducting layers on 200-mm wafers. Instead of single Nb wiring layers, it utilizes Nb/Al/Nb trilayers for each wiring layer to form Nb pillars (studs) providing vertical connections between the wires etched in the bottom layer of the trilayer and the next wiring layer that is also deposited as a Nb/Al/Nb trilayer. This technology makes possible a dramatic increase in the density of superconducting digital circuits by reducing the area of interconnects with respect to presently utilized etched contact holes between superconducting layers and by enabling the use of stacked vias. Results on the fabrication and size dependence of electric properties of Nb studs with dimensions near the resolution limit of 248-nm photolithography are presented. Superconducting critical current density in the fabricated stud-vias is about 0.3 A/μm2 and approaches the depairing current density of Nb films.