On the Feasibility of Built-In Self Repair for Logic Circuits
On the Feasibility of Built-In Self Repair for Logic Circuits
复制标题
论逻辑电路内置自修复的可行性
DOI：
10.1109/dft.2011.52
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
H. Vierhaus
中科院分区：
文献类型：
--
作者：
T. Koal;Daniel Scheit;Mario Schölzel;H. Vierhaus
根据最近对纳米集成电路故障机理的研究，它们受到磨损效应的影响，严重限制了它们的寿命。对于结合了长寿命和安全关键功能的应用，故障补偿、减压和最终自我修复的手段因此成为必须的。本文提出了一种结合逻辑电路自修复和去应力能力的电路体系结构。介绍了管理维修功能的电路。图中显示了冗余和电路重组所需的开销，具体取决于修复的粒度。最后讨论了局限性和单点故障。
According to recent investigations on fault mechanisms in nano-scale integrated circuits, they suffer from wear-out effects that limit their life time seriously. For applications that combine a long life time and safety-critical functionality, means of fault compensation, de-stressing and eventual self repair are therefore becoming a must. This paper presents a circuit architecture that combines capabilities of self repair and de-stressing for logic circuits. Circuits that administrate repair functions are introduced. The necessary overhead for redundancy as well as for circuit re-organization is shown, depending on the granularity of repair. Finally limitations as well as single points of failure are discussed.