Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs
Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs
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DOI：
10.4028/www.scientific.net/msf.527-529.1317
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发表时间：
2006-10
期刊：
影响因子：
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通讯作者：
A. Lelis;D. Habersat;G. López;J. McGarrity;F. B. McLean;N. Goldsman
中科院分区：
文献类型：
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作者：
A. Lelis;D. Habersat;G. López;J. McGarrity;F. B. McLean;N. Goldsman
我们已经观察到不稳定的阈值电压，VT，SiC金属氧化物半导体场效应晶体管（MOSFET）由于栅极偏置应力。我们已经在三种不同封装的所有4 H和6 H SiC MOSFET中常规观察到这种效应，即使在室温下也是如此。在栅极氧化物上施加约1至2 MV/cm的电场的正偏置应力持续3分钟，接着负偏置应力持续另外3分钟，通常导致ID-VGS电流-电压特性在0.25至0.5V范围内的偏移，并且是可重复的。我们推测，这种效果是由于存在大量的近界面的氧化物陷阱，推测位于氧化物过渡区，延伸到氧化物从SiC界面，由C和应变SiO2的存在下所造成的几个nm。这种不稳定性是一致的电荷隧道进出这些近界面的氧化物陷阱，这在辐照硅MOSFET已被归因于边界陷阱。观察到的SiC VT不稳定性幅度随log（时间）线性增加也与电荷隧穿一致。
We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).